Equivalent for 'event of VHDL on Verilog - Synthetizable -

I need the equivalent of VHDL incident using Verilog.

It is an example to convert Verilog from VLHDL (Note: I need both posedge and negedge in the same porosis):

  Process (CLK, I ) If start (I'event and I = 1) then // posedge x  

the end process;

I'll take a knife just after writing the code again.

It seems that you have two different things that are going on here. You have an assignment of another S. A's assignment is based on the clock and based on the basis of I is based on I.

  always @ (CLK) starts if (Pozdakke client) a < = B + 1; End always @ (in_i) if (posedge in_i) x & lt; = X + 1; Else if (negedge in_i) x & lt; = C + 2; End